Installing Icarus Simulator

1. Introduction about Icarus.

Icarus Verilog is a free compiler implementation for the IEEE-1364 Verilog hardware description language. Icarus is maintained by Stephen Williams.

Icarus Verilog is available for Linux, FreeBSD, OpenSolaris, AIX, Microsoft Windows, and Mac OS X. Released under the GNU General Public License, Icarus Verilog is free software

2. Introduction about Icarus.

Step 1 : Run sudo apt-get update from terminal.

Step 2 : Run sudo apt-get install iverilog from terminal.

Step 3 : Installing GTKWAVE software for viewing waveform. Run sudo apt-get install gtkwave.

2. Simulation Guide

Put Verilog source code path to this Makefile below and run :

make compile : compile only RTL code.

make simulate : Compile all testbench and RTL code and do simulation.

make view : Turn on waveform using GTKWAVE.

4. Example Makefile.

#———————————————————————

# ICARUS VERILOG & GTKWAVE MAKEFILE

# Guide :

#     “make compile” : compiles RTL code.

#     “make simulate” : compiles RTL+TB & simulation.

#        

#———————————————————————

#Source code directory

RTL_DIR = ../rtl

TB_DIR = ../tb

TEST = test_rd_wr_reg.v

#——————————————————————–

#RTL code

RTL_SRC = $(RTL_DIR)/async_fifo_rdctrl.v

RTL_SRC += $(RTL_DIR)/async_fifo.v

RTL_SRC += $(RTL_DIR)/async_fifo_wrctrl.v

RTL_SRC += $(RTL_DIR)/config_regs.v

RTL_SRC += $(RTL_DIR)/model_alt_ram_dual_clk.v

RTL_SRC += $(RTL_DIR)/ram_1w1r_dual_clk.v

RTL_SRC += $(RTL_DIR)/regfile8xnb.v

RTL_SRC += $(RTL_DIR)/regnb.v

RTL_SRC += $(RTL_DIR)/status_reg.v

#——————————————————————–

#TB code

TB_SRC = $(TB_DIR)/$(TEST)

TB_SRC += $(TB_DIR)/canfd_core_wrapper.v

TB_SRC += $(TB_DIR)/canfd_phy.v

TB_SRC += $(TB_DIR)/m_apb_bfm.v

#——————————————————————–

#Tools

COMPILER = iverilog

SIMULATOR = vvp

#——————————————————————-

#Tool options

COFLAGS = -v -o

SFLAGS = -v  #verbose

#——————————————————————

#Tool output

OUTPUT = out.vvp  #COMPILER OUTPUT

#——————————————————————

#PHONY

.PHONY : compile simulate

#——————————————————————

#MAKE DIRECTIVES

$(OUTPUT): $(TB_SRC) $(RTL_SRC)

      $(COMPILER) $(COFLAGS) $(OUTPUT) $(TB_SRC) $(RTL_SRC)

compile : $(RTL_SRC) $(TB_SRC)

      $(COMPILER) $(SFLAGS) $(RTL_SRC) $(TB_SRC)

simulate: $(OUTPUT)

      $(SIMULATOR) $(SFLAGS) $(OUTPUT)

view :

      gtkwave test.vcd &

clean :

      rm out.vvp test.vcd

//—————————————————

Put some code lines below to the testbench for dumping waveform.

initial

     begin

        $dumpfile(“test.vcd”);//file name of Waveform

        $dumpvars(0, canfd_core);//Name of DUT instance.

     end

5. Download example counter design.

http://www.mediafire.com/download/w09mx8f15sfgj15/counter.rar

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