Simple Counter Design

1.Design Requirements

This is a design of simple counter( Figure below) with some simple functions like that :

  • When input signals inc_i = 1’b1 and dec_i = 1’b1 then counter keep the previous value.
  • When input signals inc_i = 1’b1 and dec_i = 1’b0 then counter is increased 1.
  • When input signals inc_i = 1’b0 and dec_i = 1’b1 then counter is decreased 1.

When clr_i is asserted, counter is reset to 0.

2.Input/output Block diagram

11

3.Logic Implementation

12

-Counter Verilog Code :

////////////////////////////////////////////////////////////////////////////////
//vneetop
// Filename    : cnt.v
// Description : Simple counter
// Author      :
// Created On  : 10-6-2015
// History     : Initial
//
////////////////////////////////////////////////////////////////////////////////

module cnt
    (
    clk,
    rst_n,
    //———————————
    //Input
    inc_i,
    dec_i,
    clr_i,
    //———————————
    //Output
    cnt_o
    );

//——————————————————————————
//parameter
parameter CNT_DW  = 4’d8;

//——————————————————————————
// Port declarations
input                 clk;
input                 rst_n;
//———————————
//Input
input                 inc_i;
input                 dec_i;
input                 clr_i;
//———————————
//Output
output  [CNT_DW-1:0]  cnt_o;
//——————————————————————————
//internal signal
wire [CNT_DW-1:0]     nxt_cnt;
reg [CNT_DW-1:0]      cnt;
wire                  inc_and_dec;
//——————————————————————————
//Count logic
assign inc_and_dec = inc_i & dec_i;

                 inc_and_dec ? cnt :
                 inc_i ? (cnt + 1’b1) :
                 dec_i ? (cnt – 1’b1) :
                 cnt;
//——————————————————————————
//Flip flop
always @ (posedge clk or negedge rst_n)
    begin
    if(!rst_n)
        cnt <= 8’d0;
    else
        cnt <= nxt_cnt;
    end

assign cnt_o = cnt;

endmodule

4.Simulation with QuestaSim

14

Download and go to sim folder to run makefile.

Link : http://www.mediafire.com/file/xpg32he0iygvap6/counter.rar

 

 

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