RTL and UVM environment of HMC (Hybrid Memory Cube) controller

The HMC is memory that is built of stacked DRAM, organized in independent sections, so called vaults. Figure below shows an abstract view of the structure of an HMC. It integrates all DRAM-related management circuits and therefore off-loads the user from any DRAM timings. A single HMC features up to 4 serial links; each running with up to 16 lanes and 15 Gb/s per lane. Transactions are packetized instead of using dedicated data and address strobes. More infor mation on the HMC and its specification are available at the official Hybrid Memory Cube Consortium (HMCC) website http://www.hybridmemorycube.org



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