RTL and Verilog Testbench of SPI Wishbone Controller

24

  Introduction
The Serial Peripheral Interface (SPI) bus provides an industry standard interface between microprocessors and other devices as shown in Figure below . This reference design documents a SPI WISHBONE controller designed to provide an interface between a microprocessor with a WISHBONE bus and external SPI devices. In master mode, the SPI controller can be configured for communication with multiple off-chip SPI ports. In slave mode, the SPI supports communications with an off-chip SPI master.

http://www.mediafire.com/file/71ste4a9v5skzlb/spi_wb_master_lattice.rar

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