Synchronous FIFO Design

1. Introduction.

FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optional handshake signals for interfacing with the user logic It is often used to control the flow of data between source and destination.

FIFO can beclassified as synchronous or asynchronous depending on whether sameclock or different (asynchronous) clocks control the read and write operations. In this project the objective is to design, verify synchronous FIFO using binary coded read and write pointers to address the memory array.

 

Data flow through FIFO.

2. Functional Block Diagram and I/O.

In this example design, the FIFO depth is 16 entries and data width is 32 bit.

3. Implementation.

– Write Control Logic is used to control the write operation of the FIFO’s internal memory. It generates write address which points to the memory location where the incoming data is to be written. Write pointer is incremented by one after every successful write operation. Additionally it generates FIFO full flag which in turn are used to prevent writing data to it until wfull_o is de-asserted.

– Read Control Logic is used to control the read operation of the FIFO’s internal memory. It generates read address which points to the memory location from where the data is to be read. Read pointer is incremented by one after every successful read operation. Additionally it generates FIFO flag  which in turn are used to prevent any data read until rempty_o is de-asserted.

– When (wptr[3:0] = rptr[3:0]) the FIFO is either FULL or EMPTY. One design technique used to distinguish between full and empty is to add an extra bit to each pointer. When the write pointer increments past the final FIFO address, the write pointer will increment the unused MSB while setting the rest of the bits back to zero.The same is done with the read pointer. If the MSBs of the two pointers are different, it means that the write pointer has wrapped one more time that the read pointer. If the MSBs of the two pointers are the same, it means that both pointers have wrapped the same number of times.

– EMPTY if (wptr[4:0] = rptr[4:0]).(The fifo depth in this design is 16 entries, so waddr[3:0] and raddr[3:0] have 4 bit width,

– FULL if ({~wptr[4],wptr[3:0]} = rptr[4:0]).

– Note : The fifo depth in this design is 16 entries, so waddr[3:0] and raddr[3:0] have 4 bit width to access SRAM.

– Using n-bit pointers where (n-1) is the number of address bits required to access the entire FIFO memory buffer, the FIFO is empty when both pointers, including the MSBs are equal. And the FIFO is full when both pointers, except the MSBs are equal.

– When flush_o is 1, both read pointer and write pointer are cleared to zero.

– This figure above explain empty and full detection.

3. Write /Read Timing

-Write timing :

Read timing :

 

 

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