[Book] Computer Arithmetic Algorithms and Hardware Implementations

1 The Representation of Numbers in Computing Systems . . . . . . . 1
1.1 Information Classification . . . . . . . . . . . . . . . . . . . . . . 1
1.2 The Representation of Fixed Point Numbers . . . . . . . . . . . . 2
1.2.1 The Representation of Fixed Point Binary Numbers . . . . 2
1.2.2 The Representation of Fixed Point Decimal Numbers . . . 11
1.3 The Representation of Floating Point Numbers . . . . . . . . . . . 13


2 Functional Analysis and Synthesis of Binary and Decimal Adding
and Subtracting Devices . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.1 Serial Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.2 Parallel Adders and Subtracters . . . . . . . . . . . . . . . . . . . 25
2.2.1 Binary Adders Based on Serial Carry Propagation . . . . . 25
2.2.2 Decimal Adders Based on Serial Carry Propagation . . . . 31
2.2.3 Subtracters Based on Serial Carry/Borrow Propagation . . . 35
2.2.4 Carry-Lookahead Adders . . . . . . . . . . . . . . . . . . 38
2.2.5 Carry-Skip Adder . . . . . . . . . . . . . . . . . . . . . . 45
2.2.6 Carry-Select Adder . . . . . . . . . . . . . . . . . . . . . 49
2.2.7 Conditional-Sum Adder . . . . . . . . . . . . . . . . . . . 53
2.2.8 Carry-Save Adder . . . . . . . . . . . . . . . . . . . . . . 57
2.2.9 Binary Adders with Parity Control . . . . . . . . . . . . . 58
3 Functional Analysis and Synthesis of Binary Multiplication Devices . 67
3.1 Binary Multiplication Methods . . . . . . . . . . . . . . . . . . . 67
3.2 Sequential Sign-Magnitude Binary Multiplier . . . . . . . . . . . 70
3.3 Sequential Two’s Complement Binary Multiplier Based on
Robertson’s Procedure . . . . . . . . . . . . . . . . . . . . . . . . 78
3.4 Sequential Two’s Complement Binary Multiplier Based on
Booth’s Procedures . . . . . . . . . . . . . . . . . . . . . . . . . 83
3.5 Binary Multiplication Process Speedup by Increasing Radix Value 99
3.6 Binary Multiplication Speedup Using a Single Carry-Save Adder 104
3.7 Binary Multiplication Speedup Based on Radix 4 and a Carry-Save
Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
v
vi Contents
3.8 About “Parallelizing” of the Sequential Devices for Binary
Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
3.9 Combinational Array Structures for Binary Multiplication . . . . . 113
3.10 Combinational Tree Structures for Binary Multiplication . . . . . . 129
3.11 Other Binary Multiplication Methods . . . . . . . . . . . . . . . . 137
4 Functional Analysis and Synthesis of Binary Division Devices . . . . 143
4.1 Binary Division Methods . . . . . . . . . . . . . . . . . . . . . . 143
4.1.1 Restoring Division . . . . . . . . . . . . . . . . . . . . . . 145
4.1.2 Non-restoring Division . . . . . . . . . . . . . . . . . . . 147
4.2 Sequential Binary Divider for Unsigned Integers . . . . . . . . . . 149
4.3 Combinational Array Structures for Binary Division . . . . . . . . 154
4.3.1 Combinational Array Structure Based on Non-restoring
Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
4.3.2 Combinational Array Structure Based on Restoring
Division . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
4.4 SRT Procedures for Binary Division . . . . . . . . . . . . . . . . 163
4.4.1 Radix 2 SRT Procedure . . . . . . . . . . . . . . . . . . . 163
4.4.2 Radix 4 SRT Procedure . . . . . . . . . . . . . . . . . . . 173
4.5 Binary Division Based on Fast Convergence . . . . . . . . . . . . 185
4.5.1 The Newton-Raphson Method . . . . . . . . . . . . . . . 186
4.5.2 Goldschmidt’s Method . . . . . . . . . . . . . . . . . . . . 189
5 Functional Analysis and Synthesis of Floating Point Arithmetic
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5.1 Characteristics of the Floating Point Operation . . . . . . . . . . . 195
5.1.1 Classification of Data Processing Units . . . . . . . . . . . 195
5.1.2 Problems Regarding Floating Point Operations . . . . . . . 198
5.2 Floating Point Addition and Subtraction . . . . . . . . . . . . . . 208
5.2.1 Floating Point Addition and Subtraction Without Rounding 208
5.2.2 Floating Point Addition and Subtraction with Rounding . . 211
5.2.3 Speeding Up the Floating Point Addition/Subtraction
Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
5.3 Floating Point Multiplication and Division . . . . . . . . . . . . . 240
Appendix A Hardware Description Elements . . . . . . . . . . . . . . . 247
Appendix B Control Units Synthesis Elements . . . . . . . . . . . . . . 251
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
Link :

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