[Master thesis] Design and Implementation of a DMA Controller for Digital Signal Processor

The thesis work is conducted in the division of computer engineering at the
department of electrical engineering in Linköping University. During the thesis
work, a configurable Direct Memory Access (DMA) controller was designed and
implemented. The DMA controller runs at 200MHz under 65nm digital CMOS
technology. The estimated gate count is 26595.
The DMA controller has two address generators and can provide two clo ck
sources. It can thus handle data read and write simultaneously. There are 16
channels built in the DMA controller, the data width can b e 16-bit, 32-bit and
64-bit. The DMA controller supp orts 2D data access by configuring its intelligent
linking table. The DMA is designed for advanced DSP applications and it is not
dedicated for cache which has a fixed priority.

http://www.mediafire.com/file/of4z2sgi46nt134/Design_and_Implementation_of_a_DMA_Controller_for_digital_signal_processor.pdf

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