[Phd thesis] Configurable Architectures for Mixed High Precision Floating Point Arithmetic

Abstract :

Floating point arithmetic is widely used in many scientific and engineering computations,
numerical and signal processing applications. Its huge dynamic range and convenient
scaling of the number range provides a convenient platform for designers to realize their
algorithms. However, implementing arithmetic operations for floating point numbers in
hardware is very challenging. Also, due to increasing demand of more high precision
arithmetic, IEEE-754 floating point standard has defined and incorporated the quadruple
precision (128-bit) format, in 2008.

In view of above, a part ofthe current research work is aimed for the high performance
and area efficient architectures for floating point arithmetic, specially for double and
quadruple precision format, on FPGAs platforms, which can be easily extended for ASIC
synthesis platform. In this thesis, FPGA based architectures for double and quadruple
(high) precision multiplication and division arithmetic are proposed, which out-perform
the best available literature works, in terms of area, speed and latency.










Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s