[Master Thesis] A COMPACT CRYPTOGRAPHIC PROCESSOR FOR IPSEC APPLICATIONS

A compact cryptographic processor with custom integrated cryptographic coprocessors is
designed and implemented. The processor is mainly aimed for IPSec applications, which require intense processing power for cryptographic operations. In the present design, this processing power is achieved via the custom cryptographic coprocessors. These are an AES engine, a SHA-1 engine and a Montgomery modular multiplier, which are connected to the main processor core through a generic flexible interface. The processor core is fully compatible with Zylin Processor Unit (ZPU) instruction set, allowing the use of ZPU toolchain. A minimum set of required instructions is implemented in hardware, while the rest of the instructions are emulated in software. The functionality of the cryptographic processor and its suitability for IPSec applications are demonstrated through implementation of sample IPSec protocols in C-code, which is compiled into machine code and run on the processor. The resultant processor, together with the sample codes, presents a pilot platform for the demonstration of hardware/software codesign and performance evaluation of IPSec protocols and components.

http://www.mediafire.com/file/n2hnean2lv56nk2/A_COMPACT_CRYPTOGRAPHIC_PROCESSOR_FOR_IPSEC_APPLICATIONS.pdf

 

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