A High-Speed Unified Hardware Architecture for 128 and 256-bit Security Levels of AES and the SHA-3.

One of the five final SHA- 3 candidates, Grøs tl, has b e en ins pire d by the Advanced Encryption Standard. This unique feature can b e exploited in a large varie ty of practical applications. I n orde r to have a b e tter picture of the G røstl- AES computational efficiency (high-level scheduling, internal pipelining, resource sharing, etc.), we designed a high-s p eed copro cessor for the G røstl-based HMAC and AES in the counter mo de. This coproce ssor offers high-sp eed computations of b oth authentication and encryption with relatively small p enalty in terms of area and s p eed when compared to the authentication (original Grøstl circuitry) func tionality only. From our p ersp e ctive, the main advantage of Grøs tl over other finalists is the fact that its hardware architecture naturally accommodates AES at the cost of a small are a overhead.

http://www.mediafire.com/file/q2spmv5mvgkp8km/A_High-Speed_Unified_Hardware_Architecture_for_128_and_256-bit_Security_Levels_of_AES_and_the_SHA-3_.pdf

 

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