This thesis deals with the interoperability problems of ECC and presents the results of the development of a hardware architecture that allows to adapt dynamically its organization to operate with different parameters T. The development of such architecture is hard due the diversity of parameters T and the complexity of the underlaying algorithms. Although some reported works allow some flexibility in the choice of the ECC parameters, a reconfigurable architecture that provides interoperability with another implementation is not explored at all. An immediate application of the architecture developed is for IPSec, a security protocol where the cryptographic algorithms and its parameters are negotiated at run time. The reconfigurable computing paradigm was used in this thesis work. Due a general design methodology for reconfigurable system is not available, this thesis explores and evaluates techniques for developing interoperable ECC hardware architectures.
This thesis was developed in three stages: i) the first one consisted on the design of a base hardware architecture for evaluating several cryptographic algorithms in order to find the best circuits that produce a compact design without compromising performance; ii) the second stage consisted on providing the architecture with reconfigurability capabilities, that enable the architecture to adapt itself to different sets of parameters T at run time; iii) finally the third stage consisted on the architecture validation, which is performed by simulating the design and applying test vectors. Validation was also carried out in-circuit.
The main contributions of this thesis are: i) a hardware architecture for ECC that allows interoperability; ii) a reconfiguration strategy for developing interoperable ECC architectures; and iii) an study of finite field arithmetic algorithms performance that allows to establish a trade-off in the architecture.