[Master Thesis] A predictable and composable front-end for system on chip memory controller s


To day, verification and integration dominate the cost of developing a System-on-chip. A front-end for a predictable and composable memory controller is proposed that has the purpose to reduce verification and integration effort. The front- end acts as a scheduler for shared external memory; a back-end is required to access the memory. A predictable memory controller guarantees maximum latency and a minimum net bandwidth at design time. This allows real time requirements to be satisfied without simulation. Composability means that the service of a requestor is not affected by the behavior of other requestors. Hence , components can be verified in isolation and do not nee d to b e reverified after integration. The behavior of a back- end is abstracted by memory accesses. A predictable and composable mapping from memory accesses to SDRAM commands is proposed. Analysis of the memory accesses shows that the access granularity must b e increase d for newer memory devices to maintain high efficiency. A modular design and strict separation of concerns is essential to simplify timing analysis. When composability is required, responses are delayed such that the behavior is not affected by interference from other requestors . T he front- end is synthesized for CMOS090LP technology. The predictable front- end consumes 0.201 mm 2 for five requestors and when composability is enabled, 0.246 mm 2 is required. However, the buffers to delay the responses need 0.76 mm 2additionally



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