[Master Thesis] A Synthesizable HDL Model for Out-of-Order Superscalar Processors

Superscalar processors are at the heart of many high-performance computing platforms, either in the uniprocessor form or as processing cores in recently evolved chip multiprocessors. The superscalar microarchitecture exploits instruction-level parallelism (ILP) available in a program, by executing multiple instructions in parallel. To extract ILP, the superscalar microarchitecture forms a dynamic instruction window, and its instruction scheduler selects independent instructions out of the window for execution in a cycle. The dynamic instruction window is a segment of the dynamic instruction stream, that the processor can work upon concurrently. For issuing more than one instruction in a cycle, the scheduler goes beyond the sequential program order to find independent instructions, bringing out-of-order nature into the execution . . .

http://www.mediafire.com/file/1in5shcdwjhk9sl/A_Synthesizable_HDL_Model_for_Out-of-Order_Superscalar_Processors.pdf

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