The AHB-Lite Multi-layer Interconnect is a fully parameterized High Performance, Low Latency Interconnect Fabric soft IP for AHB-Lite. It allows a virtually unlimited number of AHB-Lite Bus Masters and Slaves to be connected without the need of bus arbitration to be implemented by the Bus Masters. Instead, Slave Side Arbitration is implemented for each Slave Port within the core.
The Multi-layer Interconnect supports Priority and Round-Robin based arbitration when multiple Bus Masters request access to the same Slave Port. Typically arbitration completes within 1 clock cycle
The RV12 is a highly configurable single-issue, single-core RV32I, RV64I compliant RISC CPU intended for the embedded market. The RV12 is a member of the Roa Logic’s 32/64bit CPU family based on the industry standard RISC-V instruction set
The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses. It features an optimizing folded 4-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
Optional features include Branch Prediction, Instruction Cache, Data Cache, and Debug Unit. Parameterised and configurable features include the instruction and data interfaces, the branch-prediction-unit configuration, and the cache size, associativity, and replacement algorithms. Providing the user with trade offs between performance, power, and area to optimize the core for the application
- Hardware architecture of the AES encryption module :
- Hardware architecture of the AES decryption module :
FIFO is a First-In-First-Out memory queue with control logic that managesthe read and write operations, generates status flags, and provides optional handshake signals for interfacing with the user logic It is often used to control the flow of data between source and destination.
The Serial Peripheral Interface (SPI) bus provides an industry standard interface between microprocessors and other devices as shown in Figure below . This reference design documents a SPI WISHBONE controller designed to provide an interface between a microprocessor with a WISHBONE bus and external SPI devices. In master mode, the SPI controller can be configured for communication with multiple off-chip SPI ports. In slave mode, the SPI supports communications with an off-chip SPI master.